Conventional optical projection lithography has been the standard silicon patterning technology for many years. It is an economical process due to its inherently high throughput, thereby providing a desirable low cost per part or die produced. A considerable infrastructure (including steppers, photomasks, resists, metrology, etc.) has been built up around this technology.
In this process, a mask, or “reticle”, includes a device pattern formed of an opaque material, such as chrome, on a transparent or semitransparent substrate. The transmission of the opaque material may also vary, such as in the case of an attenuating phase shift mask. The device pattern of the reticle can be transferred to a photoresist film using imaging techniques well known in the art. For example, a stepper that includes a light source and optics that project light coming through the reticle can be used to image the device pattern, often with, for example, a 4× to 5× reduction factor, onto a photoresist film. The photoresist can then be developed and used as a mask pattern for processing the device, as is well known in the art.
In photolithography, failing to achieve acceptable focus of the pattern during the imaging process can result in pattern defects, which can translate into device defects and possibly device failure. In some cases, the chip design itself can induce focus error. When the focus error is unacceptably high, a chip redesign may be necessary, which is a costly and time-consuming endeavor. Therefore, it is desirable to have a method and system for predicting lithography focus error that reduces the need for chip redesign.